1. Field of the Invention
The present invention relates to a semiconductor device, a semiconductor memory device, and a peripheral circuit thereof. In addition, the present invention relates to a method for driving a semiconductor memory device.
2. Description of the Related Art
In recent years, the demand for a non-volatile semiconductor memory device has been significantly increased because it has advantages in that, for example, data is not erased even when the power is turned off. In a flash memory which is a non-volatile semiconductor memory device capable of electrically erasing data at once, one memory cell can be formed using one transistor; thus, the capacity of a memory can be increased. Such a flash memory is expected to be used instead of a magnetic disk or the like.
In the above non-volatile semiconductor memory device, memory cells including MOS transistors having floating gates are arranged in matrix to form a memory cell array. Charge is accumulated in the floating gate so that the threshold value of the MOS transistor is changed. This change of threshold value is stored as data. When charge is accumulated in the floating gate, a high electric field is formed between a word line and a well formed in a substrate; thus, current which penetrates an insulating film flows from the well. As a result, charge is accumulated in the floating gate.
In general, a memory cell unit is connected to an external circuit through a signal line, and a sense amplifier latch circuit is provided therebetween. Patent Document 1 and the like disclose an example of such a structure. FIG. 19 illustrates a circuit configuration of a conventional non-volatile semiconductor memory device. The circuit in FIG. 19 includes a flip-flop circuit (FF circuit) 203. The FF circuit 203 includes a clocked inverter circuit 201 and a clocked inverter circuit 202 which are controlled by clock signals CK and CKB (inverted signal of CK), and thus has a function of holding temporarily writing data and reading data. In addition, the circuit in FIG. 19 includes a pre-charge transistor 215 which is formed using a p-channel transistor and is turned on when pre-charge operation is performed and is turned off when pre-charge operation is not performed in reading data of a memory cell. The circuit in FIG. 19 also includes a transmission circuit 213 which is connected to a bit line 214 and a node 204 on the bit line 214 side of the FF circuit 203; and a column gate 206 which is connected to a node 205 on the side opposite to the bit line side of the FF circuit 203, a data signal line 207, and a data inversion signal line 208 and which is controlled by a column control signal line 209. A memory cell unit 210 and a memory cell unit 211 are connected to the bit line 214. There is no particular limitation on the number of memory cell units in the memory cell unit 212 connected to the bit line 214. Note that only the memory cell unit connected to one bit line is illustrated in this drawing for the sake of simplicity; however, in a non-volatile semiconductor memory device which is actually used, memory cells are arrayed, and the number of circuits an example of which is illustrated in FIG. 19 corresponds to the number of bit lines.
In the circuit configuration of FIG. 19, in data writing, data is transmitted from the signal line through the column gate 206, and held temporarily in the FF circuit 203. Then, the held data is transmitted through the bit line to be written to the memory cell. In some cases, data “1” is stored in the memory cell when a high potential is applied to the bit line and data “0” is stored in the memory cell when a low potential is applied to the bit line. In data reading, data of the memory cell is temporarily held in the FF circuit 203, and the held data is transmitted through the column gate 206 to an external circuit through a signal line. In such a manner, data is read out. In some cases, the bit line has a high potential when data “0” is stored in the memory cell and the bit line has a low potential when data “1” is stored in the memory cell. That is, the potential of the bit line in data reading and that in data writing are inverted from each other. Note that the potential level set in data reading and that set in data writing are different from each other in some cases.
On the other hand, a technique in which a transistor is manufactured using an oxide semiconductor as a semiconductor material and applied to an electronic device or an optical device has attracted attention. For example, a technique in which a transistor is manufactured using zinc oxide or an In—Ga—Zn—O-based compound as a semiconductor material and used as a switching element or the like of an image display device has attracted attention.
Transistors which are manufactured using such an oxide semiconductor over a glass substrate, a plastic substrate, or the like are expected to be applied to display devices and electronic devices such as a liquid crystal display, an electroluminescent display (also referred to as an EL display), and electronic paper (see Non-Patent Document 1).